Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (known as SPI) was developed by Motorola to provide a low-cost and simple interface between microcontrollers and peripheral chips. (SPI is sometimes also known as a four-wire interface.) It can be used to interface to memory (for data storage), analog-digital converters, digital-analog converters, real-time clock calendars, LCD drivers, sensors, audio chips and even other processors. The range of components that support SPI is large and growing all the time.
Unlike a standard serial port, SPI is a synchronous protocol in which all transmissions are referenced to a common clock, generated by the master (processor). The receiving peripheral (slave) uses the clock to synchronize its acquisition of the serial bit stream. Many chips may be connected to the same SPI interface of a master. A master selects a slave to receive by asserting the slave’s chip select (also known as a slave select) input. A peripheral that is not selected will not take part in a SPI transfer.
SPI uses four main signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial CLocK (SCLK or SCK) and low-active Chip Select (CS) for the peripheral. Some processors have a dedicated chip select for SPI interfacing called Slave Select (SS). Generally, chip selects are manually driven by software for a SPI transfer, whereas a slave select will be automatically controlled by the SPI module in the processor.
MOSI is generated by the master and is received by the slave. On some chips, MOSI is labeled simply as Serial In (SI) or Serial Data In (SDI). MISO is produced by the slave, but its generation is controlled by the master. MISO is sometimes known as Serial Out (SO) or Serial Data Out (SDO) on some chips.
Unlike a standard serial port, SPI is a synchronous protocol in which all transmissions are referenced to a common clock, generated by the master (processor). The receiving peripheral (slave) uses the clock to synchronize its acquisition of the serial bit stream. Many chips may be connected to the same SPI interface of a master. A master selects a slave to receive by asserting the slave’s chip select (also known as a slave select) input. A peripheral that is not selected will not take part in a SPI transfer.
SPI uses four main signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial CLocK (SCLK or SCK) and low-active Chip Select (CS) for the peripheral. Some processors have a dedicated chip select for SPI interfacing called Slave Select (SS). Generally, chip selects are manually driven by software for a SPI transfer, whereas a slave select will be automatically controlled by the SPI module in the processor.
MOSI is generated by the master and is received by the slave. On some chips, MOSI is labeled simply as Serial In (SI) or Serial Data In (SDI). MISO is produced by the slave, but its generation is controlled by the master. MISO is sometimes known as Serial Out (SO) or Serial Data Out (SDO) on some chips.
Masters and slaves each contain a serial shift register. The master starts a transfer of a byte by writing it to its SPI shift register. As the register transmits the byte to the slave on MOSI, the slave transfers the contents of its shift register back to the master on MISO. In this way, the contents of the two shift registers are exchanged. Both a write and a read operation are performed with the slave simultaneously. SPI can therefore be a very efficient protocol.
If only a write operation is desired, the master just ignores the data it receives. Conversely, if the master just wishes to read from a slave, it must transfer a dummy byte in order to initiate a slave transmission.
Some peripherals can handle multiple byte transfers, where a continuous stream of data is shifted from the master. Many memory chips with SPI interfaces work this way. With this type of transfer, the chip select for the SPI slave must remain low for the entire duration of the transmission. For example, a memory chip might expect a “write” command to be followed by four address bytes (starting address), then the data bytes to be stored. A single transfer may involve the shifting a kilobyte or more of information.
Other slaves need only a single byte (for example, a command byte for an analog-digital converter), and some even support being daisy-chained together:
If only a write operation is desired, the master just ignores the data it receives. Conversely, if the master just wishes to read from a slave, it must transfer a dummy byte in order to initiate a slave transmission.
Some peripherals can handle multiple byte transfers, where a continuous stream of data is shifted from the master. Many memory chips with SPI interfaces work this way. With this type of transfer, the chip select for the SPI slave must remain low for the entire duration of the transmission. For example, a memory chip might expect a “write” command to be followed by four address bytes (starting address), then the data bytes to be stored. A single transfer may involve the shifting a kilobyte or more of information.
Other slaves need only a single byte (for example, a command byte for an analog-digital converter), and some even support being daisy-chained together:
In this example, the master processor transmits three bytes out of its SPI interface. The first byte is shifted into slave A. As the second byte is transferred to slave A, the first byte is shifted out of slave A and into slave B. Similarly, as the third byte is shifted into slave A, the second byte is shifted into slave B, and the first byte is shifted into slave C. If the master wishes to read a result from slave A, it must again transfer a three-byte (dummy) sequence. This will move the byte from slave A into slave B, then into slave C, and finally into the master. In the process, the master also receives bytes from slave C and slave B in turn.
Note that daisy chaining won’t necessarily work with all SPI devices, especially ones that require multi-byte transfers (such as memory chips). Again, it’s a case of checking the peripheral chips’ datasheets carefully to determine what you can and can’t do. If the datasheet doesn’t explicitly mention daisy chaining, then it’s a fair bet that the device doesn’t support it.
SPI has four modes of operation, depending on clock polarity and clock phase. For low clock polarity, the clock (SCK) is low when idle, and toggles high during a transfer. When configured for high clock polarity, the clock is high when idle, and toggles low during a transfer.
The two clock phases are known as clock phase zero and clock phase one. For clock phase zero, MOSI and MISO outputs are valid on the rising edge of the clock (SCK) if the clock polarity is low. If the clock polarity is high, these outputs are valid on the falling edge of SCK, for clock phase zero.
Conversely, for clock phase one, the opposite is true. MOSI and MISO are valid on the falling edge of the clock if clock polarity is low. They are valid on the rising edge of the clock if the clock polarity is high.
Note that daisy chaining won’t necessarily work with all SPI devices, especially ones that require multi-byte transfers (such as memory chips). Again, it’s a case of checking the peripheral chips’ datasheets carefully to determine what you can and can’t do. If the datasheet doesn’t explicitly mention daisy chaining, then it’s a fair bet that the device doesn’t support it.
SPI has four modes of operation, depending on clock polarity and clock phase. For low clock polarity, the clock (SCK) is low when idle, and toggles high during a transfer. When configured for high clock polarity, the clock is high when idle, and toggles low during a transfer.
The two clock phases are known as clock phase zero and clock phase one. For clock phase zero, MOSI and MISO outputs are valid on the rising edge of the clock (SCK) if the clock polarity is low. If the clock polarity is high, these outputs are valid on the falling edge of SCK, for clock phase zero.
Conversely, for clock phase one, the opposite is true. MOSI and MISO are valid on the falling edge of the clock if clock polarity is low. They are valid on the rising edge of the clock if the clock polarity is high.
Interfacing to SPI Devices
TBD
Communicating with SPI Devices
Learn : Interfacing : SPI