I2C Overview
I2C (Inter-Integrated Circuit) bus is a very simple, yet effective network used to interconnect peripheral devices within small-scale embedded systems. It is sometimes also known as IIC, and has been in existence for more than 30 years.
I2C uses two wires to connect multiple devices in a multi-drop bus. The bus is bi-directional, low-speed and synchronous to a common clock. Devices may be attached or detached from the I2C bus without affecting other devices. Several manufacturers, such as Microchip, Philips, Intel and others produce small microcontrollers and peripheral chips with I2C built in.
I2C uses two wires to connect multiple devices in a multi-drop bus. The bus is bi-directional, low-speed and synchronous to a common clock. Devices may be attached or detached from the I2C bus without affecting other devices. Several manufacturers, such as Microchip, Philips, Intel and others produce small microcontrollers and peripheral chips with I2C built in.
The two wires used to interconnect with I2C are SDA (serial data) and SCL (serial clock). Both lines are open-drain, meaning that the output drivers can only pull the signal line to ground. They cannot drive it high. This has the advantage that more than one device connected to a signal line may pull it low. If it were not the case, one device attempting to pull the line low while another tried to pull it high would result in a short circuit, with disastrous results. All open-drain signals need a pull-up resistor, and are low active. The idle state (when no device is asserting) is to be pulled high by the resistor. The open-drain I2C signals on your Udamonic computer are connected to a positive supply via 2K pull-up resistors and therefore remain high when not in use. A device using the I2C bus to communicate drives the lines low or leaves them pulled high as appropriate.
Each device connected to the I2C bus has a unique address and can operate as either a transmitter (a bus master) or a receiver (a bus slave), or both. I2C is a multi-master bus, meaning that more than one device may assume the role of bus master.
Both SDA and SCL are bi-directional. I2C shares the same signal line for master transmission and slave response. The timing relationship between the clock, SCL, and the data line, SDA, is simple and straightforward. When idle, both SDA and SCL are high. An I2C transaction begins with SDA going low, followed by SCL. This indicates to all receivers on the bus that a packet transmission is commencing. While SCL is low, SDA transitions (high or low) for the first valid data bit. This is known as a START condition.
Each device connected to the I2C bus has a unique address and can operate as either a transmitter (a bus master) or a receiver (a bus slave), or both. I2C is a multi-master bus, meaning that more than one device may assume the role of bus master.
Both SDA and SCL are bi-directional. I2C shares the same signal line for master transmission and slave response. The timing relationship between the clock, SCL, and the data line, SDA, is simple and straightforward. When idle, both SDA and SCL are high. An I2C transaction begins with SDA going low, followed by SCL. This indicates to all receivers on the bus that a packet transmission is commencing. While SCL is low, SDA transitions (high or low) for the first valid data bit. This is known as a START condition.
For each bit that is transmitted, the bit must become valid on SDA while SCL is low. The bit is sampled on the rising edge of SCL, and must remain valid until SCL goes low once more. Then SDA transitions to the next bit, before SCL goes high once more.
Finally, the transaction completes by SCL returning high (inactive) followed by SDA. This is known as a STOP condition.
Any number of bytes may be transmitted in an I2C packet. The most-significant bit of the packet is transmitted first. If the receiving device is unable to accept any more bytes, it can abort the transmission by holding SCL low. This forces the transmitting device to wait until SCL is released again.
Each byte transmitted must be acknowledged by the receiver. Upon the transmission of the 8th data bit, the master releases the data line SDA. The master then generates an additional clock pulse on SCL. This triggers the receiver to acknowledge the byte by pulling SDA low. If the receiver fails to pull SDA low, the master aborts the transfer and takes appropriate error-handling measures.
Each byte transmitted must be acknowledged by the receiver. Upon the transmission of the 8th data bit, the master releases the data line SDA. The master then generates an additional clock pulse on SCL. This triggers the receiver to acknowledge the byte by pulling SDA low. If the receiver fails to pull SDA low, the master aborts the transfer and takes appropriate error-handling measures.
Now, I2C is a multi-master bus. So, more than one master may attempt to start transmission at the same time. Since the bus’s default state is high, a master transmitting a 0 bit will pull SDA low, but will leave the bus in its default state if the bit is to be a 1. Thus, if two masters begin simultaneous transmission, a master leaving the bus in its default state for a 1 bit, but detecting the bus pulled low by another master (for a 0 bit), will register an error condition and abort the transmission.
Each device on an I2C bus has a unique address, and the packet transmission begins with address bits, followed by the data. An address byte consists of 7 address bits, followed by a direction bit. If the direction bit is a 0, the transmission is a write cycle and the selected slave will accept the data as input. If the direction bit is a 1, then the request is for the slave to transfer data back to the master. An example packet, transferring one byte of data, is shown below:
Each device on an I2C bus has a unique address, and the packet transmission begins with address bits, followed by the data. An address byte consists of 7 address bits, followed by a direction bit. If the direction bit is a 0, the transmission is a write cycle and the selected slave will accept the data as input. If the direction bit is a 1, then the request is for the slave to transfer data back to the master. An example packet, transferring one byte of data, is shown below:
There is a special address, known as the general call address, which broadcasts to all I2C devices. This address is %0000000 with a direction bit 0. The general call is the mechanism by which the master determines what slaves are available, and there are several types of general call. The second byte of a general call indicates the purpose of the general call to the slaves. Upon receiving the second byte, individual slaves will determine whether the command is applicable to them, and if so they will acknowledge. If the command is not applicable to a given slave, then the slave simply ignores the general call and does not acknowledge. If the second byte is $06 (%00000110), then this indicates that appropriate slaves should reset and respond with their addresses. If the second byte is $04 (%00000100), slaves respond with their addresses, but do not reset. Any other second byte of a general call, where the least significant bit is a 0, should be ignored.
If the least significant bit of the second byte is a 1, then the general call is by a master device identifying itself to other masters in the system by transmitting its own address. The other bits of the second byte contain the master’s address.
There is another special address byte, known as the START byte. This byte is %00000001 ($01). It is used to indicate to other masters that a long data transfer is beginning. This is particularly important for masters that do not have dedicated I2C hardware and must monitor the bus by software polling. When a master detects a START byte generated by another master, it can reduce its polling rate, allowing it more time for other software tasks.
I2C also supports an extended 10-bit addressing mode, allowing up to 1024 peripherals. Devices that use 7-bit addressing may be mixed with 10-bit addressing devices in a single system. In 10-bit addressing, two bytes are used to hold the address. If the (first) address byte begins with %11110XX, then a 10-bit address is being generated. The two least-significant bits of the first byte, combined with the 8-bits of the second byte, form the 10-bit address. 7-bit devices will ignore the transaction. An example packet with 10-bit addressing:
If the least significant bit of the second byte is a 1, then the general call is by a master device identifying itself to other masters in the system by transmitting its own address. The other bits of the second byte contain the master’s address.
There is another special address byte, known as the START byte. This byte is %00000001 ($01). It is used to indicate to other masters that a long data transfer is beginning. This is particularly important for masters that do not have dedicated I2C hardware and must monitor the bus by software polling. When a master detects a START byte generated by another master, it can reduce its polling rate, allowing it more time for other software tasks.
I2C also supports an extended 10-bit addressing mode, allowing up to 1024 peripherals. Devices that use 7-bit addressing may be mixed with 10-bit addressing devices in a single system. In 10-bit addressing, two bytes are used to hold the address. If the (first) address byte begins with %11110XX, then a 10-bit address is being generated. The two least-significant bits of the first byte, combined with the 8-bits of the second byte, form the 10-bit address. 7-bit devices will ignore the transaction. An example packet with 10-bit addressing:
Learn : Interfacing : I2C Overview